1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, the present invention relates to packaging for semiconductor devices.
2. Background Art
Packages combining several semiconductor components into a single package can help simplify circuit design, reduce costs, and provide greater efficiency and improved performance by keeping related and dependent circuit components in close proximity. These integrated multi-chip device packages facilitate application integration and greater performance compared to using discrete components. In particular, it is often desirable to package power devices such as IGBTs with diodes for various purposes such as circuit protection or reverse current handling.
Previously, package designs using side-by-side co-packed components have been used. However, due to the space required to co-pack each circuit component, a very large substrate is often necessary to support the package, increasing the overall package form factor. This large form factor reduces integration flexibility for space-optimized application designs. Furthermore, to implement a cost effective package, low-cost materials such as ceramics are often preferable for the substrate. Unfortunately, due to mismatched thermal expansion coefficients between ceramic substrates and attached materials such as silicon, co-pack designs using ceramic substrates are subject to heat related stresses during operation. Over time, these heat-related stresses cause solder fatigue and may eventually cause breakage and other defects, reducing long-term reliability.
Thus, a unique cost-effective, compact, and reliable solution is needed to support the efficient operation of multi-chip packages.